1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to an integrated circuit with ring oscillator.
2. Description of the Related Art
In general, a semiconductor device such as double data rate synchronous DRAM (DDR SDRAM) includes a variety of circuits to perform various circuit operations. The variety of circuits may include a ring oscillator.
FIG. 1 is a diagram illustrating a conventional ring oscillator.
The ring oscillator includes two delay cells 10_1 and 10_2 to delay an input signal and generates first to fourth oscillating clock signals φ1 to φ4. The configuration and operation of the ring oscillator are well known to those skilled in the art to which the present invention pertains. Therefore, the detailed descriptions thereof are omitted herein. The first and third clock signals φ1 and φ3 are 180 degrees out-of-phase with each other, and the second and fourth clock signals φ2 and φ4 are 180 degrees out-of-phase with each other. That is, based on the first clock signal φ1, the second clock signal φ2 has a phase difference of 90 degrees, the third clock signal φ3 has a phase difference of 180 degrees, and the fourth clock signal φ4 has a phase difference of 270 degrees.
Meanwhile, when the ring oscillator is in a clock synchronization circuit such as a phase locked loop (PLL), the clock signals φ1 to φ4 may be used as reference signals for adjusting various operation timings of the semiconductor device. Depending on cases, the phases of the clock signals φ1 to φ4 need to be shifted by a predetermined amount.